The present invention relates to mask programmable logic devices, and more particularly, to methods of creating a mask-programmed logic device from a pre-existing circuit design.
Programmable logic devices (PLDs) are well known. Early programmable logic devices were one-time configurable. For example, configuration may have been achieved by “blowing”—i.e., opening—fusible links. Alternatively, the configuration may have been stored in a programmable read-only memory. These devices generally provided a user with the ability to configure the devices for “sum-of-products” (or “P-TERM”) logic operations. Later, such programmable logic devices incorporating erasable programmable read-only memory (EPROM) for configuration became available, allowing the devices to be reconfigured.
Still later, programmable logic devices incorporating static random access memory (SRAM) elements for configuration became available. These devices, which also can be reconfigured, store their configuration information in a nonvolatile memory such as an EPROM, from which the configuration is loaded into the SRAM elements when the device is powered up. These devices generally provide the user with the ability to configure the devices for look-up table-type logic operations. At some point, such devices began to be provided with embedded blocks of random access memory that could be configured by the user to act as random access memory, read-only memory, or logic (such as P-TERM logic).
In all of the foregoing programmable logic devices, both the logic functions of particular logic resources in the device, and the interconnect resources for routing of signals between the logic resources, were programmable. Alternatively, mask-programmable logic devices have been provided. With mask-programmable logic devices, instead of selling all users the same device, a manufacturer produces a base device with a standardized arrangement of logic resources whose functions are not programmable by the user, and which lacks any routing or interconnect resources.
The user provides the manufacturer of the mask-programmable logic device with the specifications of a desired device, which may be the configuration file for programming a comparable conventional programmable logic device (“source PLD”). The manufacturer uses that information to add metallization layers to the base device described above. Those additional layers program the base device's logic resources by making certain connections within those resources, and also add interconnect resources for routing between the logic resources. Mask-programmable logic devices can also be provided with embedded random access memory blocks, as described above in connection with conventional programmable logic devices. In such mask-programmable logic devices, if the embedded memory is configured as read-only memory or P-TERM logic, that configuration is also accomplished using the additional metallization layers.
While conventional programmable logic devices allow a user to easily design a device to perform a desired function, a conventional programmable logic device invariably includes resources that may not be used for a particular design. Moreover, in order to accommodate general purpose routing and interconnect resource, conventional programmable logic devices grow ever larger as more functionality is built into them, increasing the size and power consumption of such devices. The routing of signals through the various switching resources as they travel from one routing and interconnect resource to another also slows down signals.
The advent of mask-programmable logic devices has allowed users to prove a design in a conventional source programmable logic device, but to commit the production version to a mask-programmable logic device which, for the same functionality, can be significantly smaller and use significantly less power, because only the interconnect and routing resources actually needed for the particular design are added to the base device. In addition, there are no general purpose switching resources consuming space or power, or slowing down signals.
However, mask-programmable logic devices do not contain predefined functional logic resources or routing resources. Therefore, the task of programming the customized logic resources and creating the customized interconnect resources for each design falls to the manufacturer in migrating the design of the user's source device to a mask-programmable device. This task is time consuming, and significantly slows down the process of migrating the design and delivering it to the user. The migration process is further complicated by the fact that certain implementation-related problems such as functionality, timing, testability violations, and signal attenuation are not apparent until after an initial mask-programable device is fabricated and tested. Fixing such problems often requires the generation of test benches, test vectors, or timing and functional simulations on the part of the user, and the redesign of the custom interconnect and/or reallocation of logic resources on the base device. One problem with this solution, however, is that it often requires the fabrication of multiple devices to prove a given design and is therefore costly and time consuming.
Accordingly, it would be desirable to provide a method for efficiently implementing a pre-existing circuit design in a mask-programmable device that requires minimal user involvement.